TimingAnalyzer - Timing diagrams and performing timing analysis

Wednesday, 17 March 2010 21:32

The TimingAnalyzer can be used to easily draw timing diagrams and perform timing analysis to find faults in digital systems. The diagrams can be saved in many different image file formats and scalable vector formats so they can easily be added to documentation such as specifications, data sheets, technical manuals, and presentations. The diagrams are saved as simple text files that can be easily distributed to other users. With Python/Shell scripts, the user can customize the program (add new features or functions to the TimingAnalyzer) or use the included scripts to draw large complex timing diagrams quickly, generate test vectors for analog and digital simulations, build test-benches. The scripts are executed while the program is running. Some features are:

Generate timing diagrams directly from VHDL or Verilog Simulations;
Generate timing diagrams directly from VCD files. GtkWave is a VCD viewer and more; you can quickly convert VCD diagrams to timing diagrams using a menu selection;
Timing analysis with minimum, typical, maximum, and min-max delay margins;
Save diagrams as JPG, GIF, PNG image files, and PS, PDF, and SVG formats.

It's written in the Java programming language then you launch it with command java -jar TimingAnalyzer.jar. For more information about TimingAnalyzer click here.