Alliance - VLSI Design Layout and Checks

Saturday, 27 December 2008 18:02

Alliance is a complete set of free CAD tools and cell libraries for VLSI design. It includes a VHDL compiler and simulator, logic synthesis tools, and automatic place and route tools. A complete set of portable CMOS libraries is provided. It covers a wide range of the standard design flow (from VHDL up to layout). Alliance is the result of a twelve year effort spent at ASIM department of LIP6 laboratory of the Pierre et Marie Curie University (Paris VI, France). It includes;

VHDL Compilation and Simulation;
Model checking and formal proof;
RTL and Logic synthesis;
Data-Path compilation;
Macro-cells generation;
Place and route;
Layout edition;
Netlist extraction and verification;
Design rules checking (DRC).

Alliance has been used for research projects such as the 875.000 transistors StaCS superscalar microprocessor and 400.000 transistors IEEE Gigabit HSL Router. It's enclosed on Fedora Electronic Laboratory project, Fedora Electronic Lab live DVD.