Elettrolinux

TkGate is a graphical editor and event-driven simulator for digital circuits with a tcl/tk-based interface. Supported circuit elements include basic gates (AND, OR, etc.), tri-state gates, adders, multipliers, registers, memories and mos transistors, also includes ttys and modules for hierarchical design. The TkGate simulator, called VERGA (VERilog simulator for GAte), is a discrete time simulator with time advancing in discrete units called "epochs". All delay must be an integer number of epochs. The simulator supports continuous simulation, single step simulation (by clock or epoch) and breakpoints. The Verga simulator is normally used through the TkGate interface, but it can also be run by itself directly on text Verilog files. The simulator can be controlled either interactively or through a simulation script. Memory contents can be loaded from files, and a microcode/macrocode compiler (gmac) is included to create TkGate memory files from a high-level description. Gmac is a simple microcode and macrocode compiler which can be used to create memory files for TkGate. You can write declarations to define your own microcode and macrocode. The current version of Gmac is fairly simple; no attempt is made to handle arbitrary instruction sets with complex addressing modes, but it should be sufficient to create simple micro and macro programs. TkGate saves files in a Verilog-like format. TkGate supports a subset of the complete Verilog specification. For more information click here